The subject matter disclosed herein relates to silicon carbide semiconductor devices and, more specifically, to silicon carbide semiconductor devices for power applications.
During fabrication of a semiconductor device, such as a field-effect transistor (FET), one or more contacts may be formed (e.g., in a contact region of a FET device). In general, it may be desirable for a contact to have a low resistance (e.g., an ohmic contact) when constructing, for example, a contact via in a silicon carbide FET device. Additionally, during the construction of these low-resistance contacts, certain semiconductor device manufacturing techniques (e.g., lift-off technique) may lead to defects in the resulting device structure (e.g., rough edges, stringers, torn contacts, undesired excess metal, poor adhesion, and/or other forms of damage to the device). Furthermore, other device manufacturing techniques (e.g., self-aligning techniques), including methods that work well for constructing silicon devices, often do not prove to be effective for constructing silicon carbide devices.